My understanding is that a Linode runs as a single process on the host, so that even if the host has a snazzy new 1024-core WhizBang, Inc. "CPU Of The Future" I would be able to use at most use 1/(# of cores) of the host CPU resources. Is this correct, or would UML or Xen parcel out multi-core resources?

I ask as there is so much buzz about multi-core CPU's in the trade rags these days, and of course my site is such a CPU hog - it had both feet in the trough this morning all right.

James

Linode has run on SMP dual xeons from the start. The only caveat is that each linode user can run one process at a time due to UML restrictions.

UML is actually split into four threads on the host -- kernel, userspace, disk I/O thread, and an interrupts thread (I think). So, technically, UML still benefits from an SMP-host, but only slightly -- since if the kernel thread is using CPU the userspace thread is sleeping, effectively single-threading UML.

Jeff Dike has working UML-SMP patches in his queue, awaiting refinement. Each virtual CPU inside UML will add another process on the host, so a multi-processor UML will be able to take advantage of CPUs on the host. Future Linodes will have this enabled by default.

-Chris

> Each virtual CPU inside UML will add another process on
> the host, so a multi-processor UML will be able to take
> advantage of CPUs on the host. Future Linodes will have
> this enabled by default.

Hmmm, this won't help us CPU hogs too much. I'm changing my site code to parallelize the internal computations at some point, so (if my wife doesn't kill me) I may have to (choke) purchase (cough) a multi-core server of some kind to benefit from future hardware (cough, choke).

James

P.S. I'm switching to Trilinos from the Sandia National Laboratories (http://software.sandia.gov) - it will run serially for now and I'll recompile with parallelization enabled when I can access the necessary hardware.

http://arstechnica.com/news.ars/post/20060926-7840.html

Here is data on the Intel '80 cores on one chip' demo - 1.2 teraFLOPS (drool, drool). Looks like all the big CPU manufacturers are heading in this direction, although how these computing resources will parceled out in virtualized servers of the future is anyone's guess. Unlike Cell they don't have high-speed silicon memory connections and so Intel wil use lasers to shuttle data for memory I/O.

I just hope massively multi-cores get cheap enough for me to afford. One - just one - Cell+ due out end-o-'07 would be awesome for me as I could tune my code to use the SPE's effectively - and you can already buy dual-Cell blades from IBM ($18 grand cough choke) and a dual Cell+ should be a very, very serious contender in the HPC market.

James